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0.4 CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP Packages ADG888
FEATURES
1.8 V to 5.5 V operation Ultralow on resistance 0.4 typical 0.6 maximum at 5 V supply Excellent audio performance, ultralow distortion 0.07 typical 0.14 maximum RON flatness High current carrying capability 400 mA continuous 600 mA peak current at 5 V Automotive temperature range: -40C to +125C Rail-to-rail switching operation Typical power consumption (<0.1 W)
FUNCTIONAL BLOCK DIAGRAM
ADG888
S1A D1 S1B S2A D2 S2B IN1 S3A D3 S3B S4A D4 S4B IN2
05432-001
APPLICATIONS
Cellular phones PDAs MP3 players Power routing Battery-powered systems PCMCIA cards Modems Audio and video signal routing Communication systems Data switching
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
GENERAL DESCRIPTION
The ADG888 is a low voltage, dual DPDT (double-pole, double-throw) CMOS device optimized for high performance audio switching. With its low power and small physical size, it is ideal for portable devices. This device offers ultralow on resistance of less than 0.8 over the full temperature range, making it an ideal solution for applications requiring minimal distortion through the switch. The ADG888 also has the capability of carrying large amounts of current, typically 400 mA at 5 V operation. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The ADG888 exhibits break-before-make switching action. The ADG888 is available in a 16-ball WLCSP, 16-lead LFCSP, and a 16-lead TSSOP. These packages make the ADG888 the ideal solution for space-constrained applications.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. <0.6 over full temperature range of -40C to +125C. High current handling capability (400 mA continuous current at 5 V). Low THD + N (0.008% typical). Tiny 16-ball WLCSP, 16-lead LFCSP, and 16-lead TSSOP.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADG888 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution...................................................................................5 Pin Configurations and Function Descriptions ............................6 Typical Performance Characteristics ..............................................7 Test Circuits........................................................................................9 Terminology .................................................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 13
REVISION HISTORY
12/06--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 5 Changes to Ordering Guide .......................................................... 13 7/05--Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG888 SPECIFICATIONS
VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON tOFF Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk +25C B Version 1 Y Version1 0 to VDD 0.4 0.48 0.04 0.06 0.07 0.11 0.2 0.2 2.0 0.8 0.005 0.1 2 22 30 13 17 9 70 -67 -99 -67 Total Harmonic Distortion (THD + N) Insertion Loss -3 dB Bandwidth CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.008 -0.03 29 58 110 0.003 1
1 2
Unit V typ max typ max typ max nA typ nA typ V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ % dB typ MHz typ pF typ pF typ A typ A max
Test Conditions/Comments
0.55
0.6
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA See Figure 16 VDD = 4.2 V, VS = 2.2 V, IDS = 100 mA
0.07 0.13
0.075 0.14
VDD = 4.2 V, VS = 0 V to VDD IDS = 100 mA VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 17 VS = VD = 1 V or 4.5 V; see Figure 18
VIN = VINL or VINH
33 18
35 19 5
RL = 50 , CL = 35 pF VS = 3 V/0 V; see Figure 19 RL = 50 , CL = 35 pF VS = 3 V/0 V; see Figure 19 RL = 50 , CL = 35 pF VS1 = VS2 = 3 V; see Figure 20 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 21 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 22 Adjacent channel; RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 25 Adjacent switch; RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 23 RL = 32 , f = 20 Hz to 20 kHz, VS = 3 V p-p RL = 50 , CL = 5 pF; see Figure 24 RL = 50 , CL = 5 pF; see Figure 24
VDD = 5.5 V Digital inputs = 0 V or 5.5 V
4
Temperature range for the Y version is -40C to +125C for the TSSOP and LFCSP; temperature range for the B version is -40C to +85C for the WLCSP. Guaranteed by design, not production tested.
Rev. A | Page 3 of 16
ADG888
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage IS (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON tOFF Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk +25C B Version 1 Y Version1 0 to VDD 0.5 0.7 0.045 0.072 0.16 0.75 0.8 Unit V typ max typ max typ max nA typ nA typ 1.3 0.8 0.005 0.1 2 28 43 13 20 14 50 -67 -99 -67 Total Harmonic Distortion (THD + N) Insertion Loss -3 dB Bandwidth CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.01 -0.04 29 60 115 0.003 1
1 2
Test Conditions/Comments
VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA; see Figure 16 VDD = 2.7 V, VS = 1 V IS = 100 mA VDD = 2.7 V, VS = 0 V to VDD IS = 100 mA VDD = 3.6 V VS = 1 V/2.6 V, VD = 2.6 V/1 V; see Figure 17 VS = VD = 1 V or 2.6 V; see Figure 18
0.077
0.083 0.262
0.2 0.2
V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ VIN = VINL or VINH
47 21
50 22 5
2
RL = 50 , CL = 35 pF; see Figure 19 VS = 1.5 V/0 V RL = 50 , CL = 35 pF; see Figure 19 VS = 1.5 V/0 V RL = 50 , CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 20 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 21 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 22 Adjacent channel; RL = 50 V, CL = 5 pF, f = 100 kHz; see Figure 25 dB typ Adjacent switch; RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 23 % RL = 32 , f = 20 Hz to 20 kHz, VS = 1 V p-p dB typ RL = 50 , CL = 5 pF; see Figure 24 MHz typ RL = 50 , CL = 5 pF; see Figure 24 pF typ pF typ VDD = 3.6 V A typ Digital inputs = 0 V or 3.6 V A max
Temperature range for the Y version is -40C to +125C for the TSSOP and LFCSP; temperature range for the B version is -40C to +85C for the WLCSP. Guaranteed by design, not production tested.
Rev. A | Page 4 of 16
ADG888 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND Analog Inputs, Digital Inputs1 Peak Current, S or D 5 V operation Continuous Current, S or D 5 V operation Operating Temperature Range Automotive (Y Version) TSSOP and LFCSP packages Industrial (B version) WLCSP package Storage Temperature Range Junction Temperature 16-Lead TSSOP Package JA Thermal Impedance (4-Layer Board) JC Thermal Impedance 16-Lead WLCSP Package JA Thermal Impedance (4-Layer Board) 16-Lead LFCSP Package JA Thermal Impedance (4-Layer Board) Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature
1
Rating -0.3 V to +6 V -0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 600 mA (pulsed at 1 ms, 10% duty cycle max) 400 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
-40C to +125C -40C to +85C -65C to +150C 150C 112C/W 27.6C/W 130C/W
30.4C/W
260(+0/-5)C 10 sec to 40 sec
Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to the maximum ratings given.
Rev. A | Page 5 of 16
ADG888 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL A1 INDICATOR A D4 1 S4B 2 S3B 3
05432-002
B S4A
C S1A
D D1
16 S1A 14 GND 15 VDD 13 S4A
GND
VDD
S1B
VDD S1A
1 2 3 4 5 6 7 8
16 15
GND S4A D4 S4B S3B D3 S3A IN2
05432-004
IN2
IN1
S2B
D1 1
D3 S3A S2A D2
PIN 1 INDICATOR
12 D4 11 S4B 10 S3B 9 D3
D1 S1B S2B D2 S2A
05432-003
ADG888
TOP VIEW (Not to Scale)
14 13 12 11 10 9
S1B 2 S2B 3 D2 4 TOP VIEW
4
S2A 5
S3A 8
TOP VIEW (BALL SIDE DOWN) Not to Scale (SOLDER BALLS ON OPPOSITE SIDE)
IN1 6
IN2 7
IN1
Figure 2. 16-Ball WLCSP Pin Configuration
Figure 3. 16-Lead LFCSP Pin Configuration
Figure 4. 16-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
WLCSP Ball No. 2C 2B 1B, 1C, 2A, 2D, 3A, 3D, 4B, 4C 1A, 1D, 4A, 4D 3B, 3C LFCSP Pin No. 15 14 2, 3, 5, 8, 10, 11, 13, 16 1, 4, 9, 12 6, 7 TSSOP Pin No. 1 16 2, 4, 5, 7, 10, 12, 13, 15 3, 6, 11, 14 8, 9 Mnemonic VDD GND S D IN Description Most Positive Power Supply Potential. Ground (0 V) Reference. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input.
Table 5. Truth Table
Logic (IN1/IN2) 0 1 Switch 1A/2A/3A/4A Off On Switch 1B/2B/3B/4B On Off
Rev. A | Page 6 of 16
ADG888 TYPICAL PERFORMANCE CHARACTERISTICS
0.40 VDD = 4.2V 0.35 VDD = 4.5V 0.30 0.25 0.20 0.15 0.10
05432-005
TA = 25C IDS = 100mA
0.7 TA = +125C TA = +85C
VDD = 3V IDS = 100mA
0.6
0.5
VDD = 5.5V
RON ()
RON ()
VDD = 5V
0.4 TA = +25C TA = -40C
0.3
0.2
0 0 1 2 3 VS, VD (V) 4 5
0 0 0.5 1.0 1.5 VS, VD (V) 2.0 2.5 3.0
Figure 5. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V
Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3 V
400 TA = 25C 350 300
0.6 VDD = 2.7V 0.5 VDD = 3V
TA = 25C IDS = 100mA
0.4
VDD = 5V 250
QINJ (pC)
RON ()
0.3
VDD = 3.3V VDD = 3.6V
200 150
0.2
100
0.1
05432-006
05432-009
50 0 0 0.5 1.0 1.5
VDD = 3V
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VS, VD (V)
2.0
2.5 3.0 VD (V)
3.5
4.0
4.5
5.0
Figure 6. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V
Figure 9. Charge Injection vs. Source Voltage
0.45 0.40 0.35 0.30 TA = +125C
VDD = 5V IDS = 100mA
45 40 35 30
TIME (ns)
VDD = 3V; SxA CHANNELS VDD = 3V; SxB CHANNELS VDD = 5V; SxA CHANNELS VDD = 5V; SxB CHANNELS
TA = +85C TA = +25C TA = -40C
RON ()
0.25 0.20 0.15 0.10 0.05 0 0 0.5 1.0 1.5 2.0
25 20 15 10
tON
tOFF VDD = 3V, 5V; SxB CHANNELS VDD = 3V, 5V; SxA CHANNELS
05432-007
5 0 -40
2.5
3.0
3.5
4.0
4.5
5.0
-20
0
VS, VD (V)
20 40 60 TEMPERATURE (C)
80
100
120
Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V
Figure 10. tON/tOFF Times vs. Temperature
Rev. A | Page 7 of 16
05432-010
05432-008
0.05
0.1
ADG888
0 -1 -2 0.020 VDD = 5V, VS = 4V p-p 0.025 VDD = 3V, VS = 2V p-p TA = 25C
ON RESPONSE (dB)
-3 THD + N (%) -4 -5 -6 -7 -8 -9
05432-011
0.015
0.010
VDD = 3V, VS = 1V p-p VDD = 5V, VS = 3V p-p
0.005 TA = 25C VDD = 3V, 4.2V, 5V 100k 1M FREQUENCY (Hz) 10M
VDD = 3V, VS = 0.5V p-p VDD = 5V, VS = 1V p-p
05432-014
-10 10k
0 0 2k 4k 6k 8k 10k 12k 14k FREQUENCY (Hz) 16k 18k
100M
20k
Figure 11. Bandwidth
Figure 14. Total Harmonic Distortion + Noise (THD + N)
0
TA = 25C VDD = 3V, 4.2V, 5V
20
-20
0
TA = 25C VDD = 3V, 4.2V, 5V NO DECOUPLING ON SUPPLIES
ATTENUATION (dB)
-40
ATTENUATION (dB)
05432-012
-20
-60
-40
-80
-60
-100
-80
05432-023
-120 100
1k
10k
100k
1M
10M
100M
-100 100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. Off Isolation vs. Frequency
Figure 15. AC PSRR
0 -20
TA = 25C VDD = 3V, 4.2V, 5V ADJACENT CHANNELS (S1A-S2A)
-40
ATTENUATION (dB)
ADJACENT SWITCHES (S1A-S1B)
-60 -80 -100 S1A-S4A
05432-013
-120 -140 100
1k
10k 100k 1M FREQUENCY (Hz)
10M
100M
Figure 13. Crosstalk vs. Frequency
Rev. A | Page 8 of 16
ADG888 TEST CIRCUITS
IDS V1 S VS RON = V1/IDS D
05432-015
ID (ON) VD
05432-017
NC
S
D
A
Figure 16. On Resistance
Figure 18. On Leakage
IS (OFF) A VS
S
D
ID (OFF) A VD
05432-016
Figure 17. Off Leakage
VDD 0.1F
VDD VS S1B S1A D1 RL 50 GND VOUT CL 35pF VOUT VIN 50% 50%
IN
90%
90%
05432-018
tON
tOFF
Figure 19. Switching Times, tON, tOFF
VDD 0.1F 50% VDD VS S1B S1A D1 RL IN GND 50 CL 35pF VIN VOUT VOUT 80% 80% 0V 50%
tBBM
tBBM
05432-019
Figure 20. Break-Before-Make Time Delay, tBBM
VDD SW ON S1B VS IN GND D1 S1A 1nF VOUT VOUT
05432-020
SW OFF
VIN NC VOUT
QINJ = CL VOUT
Figure 21. Charge Injection
Rev. A | Page 9 of 16
ADG888
VDD 0.1F NETWORK ANALYZER 50 VS
D 0.1F NETWORK ANALYZER 50 VS VOUT
05432-022
VDD
VDD
VDD
NC
S1B D
S1A
50
S1B
S1A
05432-021
RL 50 GND
VOUT
GND
RL 50
OFF ISOLATION = 20 log
VOUT VS
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 22. Off Isolation
Figure 24. Bandwidth
VDD 0.1F
VDD VOUT S1A RL 50 50 VS GND
NETWORK ANALYZER VOUT 50 S2A NC S2B D1 50 D2 NC
S1B
D
RL 50
50 VS
05432-024
S1A NC S1B
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
Figure 23. Channel-to-Channel Crosstalk (S1A to S1B)
Figure 25. Channel-to-Channel Crosstalk (S1A to S2A)
Rev. A | Page 10 of 16
05432-025
ADG888 TERMINOLOGY
IDD Positive supply current. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between Terminal D and Terminal S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. RON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and the 90% points of the digital input and switch on condition. tOFF Delay time between the 50% and the 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. This is specified for two conditions: * * Adjacent channel, that is, S1A to S2A, S1B to S2B, S3A to S4A, or S3B to S4B. Adjacent switch, that is, S1A to S1B, S2A to S2B, S3A to S3B, or S4A to S4B.
-3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitudes plus signal noise to the fundamental.
Rev. A | Page 11 of 16
ADG888 OUTLINE DIMENSIONS
0.65 0.59 0.53 SEATING PLANE BALL 1 IDENTIFIER 2.06 2.00 SQ 1.94 0.50 BALL PITCH 0.36 0.32 0.28
D C B A 1
2
3
4
TOP VIEW
(BALL SIDE DOWN)
Figure 26. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16) Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX 0.60 MAX
13 12 16 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC
PIN 1 INDICATOR
TOP VIEW
0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50
EXPOSED PAD
(BOTTOM VIEW)
9 8 5
4
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 28. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters
Rev. A | Page 12 of 16
111105-0
0.28 0.24 0.20
0.11 0.09 0.07
BOTTOM VIEW
(BALL SIDE UP)
ADG888
ORDERING GUIDE
Model ADG888YRUZ 2 ADG888YRUZ-REEL2 ADG888YRUZ-REEL72 ADG888YCPZ-REEL2 ADG888YCPZ-REEL72 ADG888BCBZ-REEL2 ADG888BCBZ-REEL72 EVAL-ADG888EB
1 2
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +85C -40C to +85C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board
Package Option RU-16 RU-16 RU-16 CP-16-4 CP-16-4 CB-16 CB-16
Branding 1
S0D S0D S02 S02
Branding on these packages is limited to three characters due to space constraints. Z = Pb-free part.
Rev. A | Page 13 of 16
ADG888
NOTES
Rev. A | Page 14 of 16
ADG888
NOTES
Rev. A | Page 15 of 16
ADG888
NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05432-0-12/06(A)
Rev. A | Page 16 of 16

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